During the procedure of laying out the paths of bitlines and column address selection leads in a dynamic random access memory (DRAM), a designer considers the effect of parasitic capacitance between adjacent leads, such as bitlines and column address selection leads, which run parallel to one another. Because bitlines typically carry very small signals, the effects of parasitic capacitance are very important and must be distributed with great care to assure proper operation of the memory devices. In this regard, it is important that every bitline should have very nearly the same amount of parasitic capacitance as every other bitline. The total of all parasitic capacitance for all of the bitlines should be minimized to conserve power consumption.
In the prior art, the column address selection lead over most of its length is laid out wide enough to overlap both leads of a bitline and thereby equally distribute parasitic capacitance between the two leads of the bitline. In this writing, the term overlap refers to the width of the selection lead being wide enough to cover both leads of a bitline.
Because only one column address selection lead was used with every two bitlines, a special layout was designed. Each column address selection lead has been routed to overlay one bitline for half the distance across the array and to overlay the second bitline across the other half of the array. The column address selection leads are routed around metal straps used for bitline twists, or crossovers. Overlay refers to the length of the address selection lead that runs parallel with a bitline.
In a later prior art design concept, four bitlines are addressed by a single column address selection lead. This leaves one surplus column address selection lead for every four bitlines. Because of the need for equal parasitic capacitance for every bitline, the surplus column address selection leads have been left in place on the memory device. These surplus leads maintain the magnitude of parasitic capacitance of the prior art and thereby cause a continuing high level of power consumption. Each surplus lead may potentially cause the device to be defective because of the close proximity to other active leads. There is a single bitline width, or pitch, between adjacent column address selection leads.
It is a problem to remove the excess parasitic capacitance and increase the column address selection lead spacing without disturbing the balance of parasitic capacitance among the bitlines.